Transistors are the building blocks of modern electronics, used in everything from televisions to laptops. As transistors have gotten smaller and more compact, so have electronics, which is why your cell phone is a super powerful computer that fits in the palm of your hand.
But there's a scaling problem: Transistors are now so small that they are difficult to turn off. A key device element is the channel that charge carriers (such as electrons) travel across between electrodes. If that channel gets too short, quantum effects allow electrons to effectively jump from one side to another even when they shouldn't.
One way to get past this sizing roadblock is to use layers of 2D materials—which are only a single atom thick—as the channel. Atomically thin channels can help enable even smaller transistors by making it harder for the electrons to jump between electrodes. One well-known example of a 2D material is graphene, whose discoverers won the Nobel Prize in Physics in 2010. But there are other 2D materials, and many believe they are the future of transistors, with the promise of scaling channel thickness down from its current 3D limit of a few nanometers (nm, billionths of a meter) to less than a single nanometer thickness.
Though research has exploded in this area, one issue has been persistently overlooked, according to a team of scientists from the National Institute of Standards and Technology (NIST), Purdue University, Duke University, and North Carolina State University. The 2D materials and their interfaces—which researchers intend to be flat when stacked on top of each other—may not, in fact, be flat. This non-flatness in turn can significantly affect device performance, sometimes in good ways and sometimes in bad.
In a new study published in the April 26, 2022, issue of ACS Nano, the research team reports the results of their measurements of the flatness of these interfaces in transistor devices that incorporate 2D materials. They are the first group to take high-resolution microscopy images showing flatness of these 2D layers in complete device arrays, on a relatively large scale—about 12 micrometers (millionths of a meter) as opposed to the more common 10-nm to 100-nm range.
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